The present invention relates generally to an apparatus and method for etching a surface of a semiconductor material without disturbing the flow pattern defect distribution on the surface. More particularly, the invention relates to an apparatus and method which enable accurate determination of flow pattern defects at any position on the surface of a semiconductor material.
When a silicon crystal is grown, vacancies are formed where a silicon atom is missing from the crystal matrix. These vacancies are believed to coalesce at certain temperatures forming defects throughout the single crystal. The grown-in defects resulting from a collection of vacancies include flow pattern defects (FPDs) also known as D defects. These defects adversely affect properties of devices formed from the silicon wafers, such as gate oxide integrity.
Flow pattern defects on the surface of a silicon wafer are not detectable until the wafer has been subjected to an etching process. Silicon wafers are typically placed within an etch basket that is immersed in a tank filled with a Secco etching solution. The front and back surfaces of each of the wafers are positioned vertically within the etch tank. As the etching occurs, the chemical reaction nucleates a bubble at each defect on the front wafer surface (i.e., the surface of the wafer which is to be analyzed). The bubble grows as reaction products are formed and eventually breaks away from the defect site and floats upwardly along the surface of the wafer. This causes a V-shaped pattern to form on the surface as the bubble grows and travels upwardly. The tip of the V-shaped pattern marks the location of the defect on the surface. The V-shaped flow patterns can be identified under magnification and provide a quantitative measurement of the flow pattern defect density within the semiconductor material.
When the flow patterns are analyzed, the density of V-shaped patterns significantly and continuously decreases from the lower half of the wafer to the top half of the wafer (i.e., from point 5 to point 1 as shown in FIG. 5). This variation in defect density across the front wafer surface is recognized as an artifact of the etching process but the cause of the variation is unknown. Recognizing this problem, the current practice is to average the number of defects found at a plurality of locations on the wafer surface to estimate an approximate flow pattern defect density.
As a result of the present invention, it is now believed that the density variation is caused by interferences on the front surface of a silicon wafer during the etching process. As a bubble moves upwardly along the wafer surface, it can interfere with the bubbles which are being formed on the surface above it and can dislodge these bubbles before they have caused the characteristic flow pattern to form. These disturbances generally result in a lower flow pattern density for points uppermost on the front surface of the wafer. The flow patterns formed during etching are therefore dictated by the etching process rather than the actual defect distribution on the wafer surface. Additionally, as the bubbles at the bottom of a wafer surface travel upward, the etchant at the surface is carried upward by the bubbles, resulting in nonuniform removal of silicon from the wafer surface.
Integrated circuit manufacturers are beginning to require silicon wafers having less than 100 flow pattern defects per square centimeter. As more stringent defect standards are required by the industry, the accuracy of defect detection must improve. There is a need for an etching process which facilitates accurate determination of flow pattern defects at any point on the front surface of a silicon wafer and therefore a more accurate determination of the bulk density of grown-in defects. The crystal growth process can then be modified to minimize grown-in defects in subsequent silicon single crystals.